The present invention relates to an information processing system and an encryption/decryption system and, in particular, to an information processing system that is capable of performing computation to any desired precision due to the hardware configuration thereof and an encryption/decryption system that is capable of performing encryptions and decryptions due to the hardware configuration thereof. In addition, the present invention also relates to an information processing system, a system LSI, and electronic equipment that use an internal or external bus line for an optical transmission method.
When complicated and large-scale computations are to be performed, such as those for random number generation, wavelet transformation, neural networks, fast Fourier transformation, and digital filters, considerations of development costs and time scales make it standard in the art to implement them by software, using general-purpose computation devices, instead of dedicated hardware which is only used in specific applications.
The recent spread of the Internet has increased the necessity of information security techniques, from the viewpoints of electronic transactions and privacy protection, and cryptographic techniques have drawn attention as effective means of providing them.
The main categories of cryptographic methods are private-key cryptosystem and public-key cryptosystem, where a typical private-key cryptosystem is the Data Encryption Standard (DES) and a typical public-key cryptosystem is Rivest-Shamir-Adleman cryptography (RSA) system.
In principle, DES is a method of rearranging or substituting of a data bit string and RSA is a method of performing residue operations on an extremely large number of bits, so a public-key cryptosystem tends to be several hundred times slower than a private-key cryptosystem. This is because public-key cryptosystems perform residue computations to an extremely high precision, using at least several hundred bits as a modulus.
In such a case, it has become common to use a cryptographic method in which a private-key cryptosystem is used to encrypt a large-volume data string and a public-key cryptosystem is used for delivering authentication, a signature, and a key, which involve a small volume of data.
With public-key cryptosystem, the encryption strength can be selected by varying the bit length of the key, so there is a demand for methods of enabling computations using public keys of various different numbers of bits that have been revealed to communications partners.
If it is desired to exceed the arithmetic precision of a general-purpose computation device, when using a technique of employing such a general-purpose computation device to implement computations by software, such as those used in random number generation, wavelet transformation, neural networks, fast Fourier transformation, and digital filters, it is necessary to support everything in the software and thus it may become impossible to implement this in reality because of increases in programming labor and processing time.
It is regulated that DES must be implemented by using hardware techniques. Therefore, it is in fact difficult to prevent third parties from breaking the ciphers of an encryption/decryption system created by software alone. If part of the encryption algorithm could be implemented by hardware, it will be possible to increase the strength of the encryption.
A single chip public-key cryptographic processor has already been proposed, similar to this public-key cryptosystem (in the proceedings of the Electronic Information Communications Society, D-I, Vol. J80-D-I, No. 8, pp. 725-735, 1997-8).
However, although this single chip public-key cryptographic processor does enable processing at any desired precision within a precision range that is set beforehand by the hardware, processing at a precision in excess of that preset precision is not possible, raising the problem that new hardware must be designed therefor.
If the computation device is configured of thin film transistors (TFTs) on a single chip, by way of example, the presence of non-operating transistors could make the entire computation device unusable, raising problems of a reduction in yield and also an increase in fabrication costs.
As yet another technical concern, recent advances in microcomputers has promoted the miniaturization and value-added capabilities of appliances in various fields, but it has become extremely difficult to design such microcomputers. Together with the push for increases integration of microcomputers formed of microprocessors (MPUs) on single chips, wiring widths are now of the submicron order and the resistance thereof is increasing, and also the stray capacities thereof have been increased by multi-layer configurations, so that distributed parameter circuits are formed in the wiring sections, which increased the propagation delays in electrical signals.
This means that it is necessary to determine the instruction cycle of the central processing unit (CPU) within the microcomputer, after considering the time required for the CPU to transmit data and addresses to other functional units and the time required before the CPU can input data from the other functional units, which increases the design load caused by signal propagation delays.
Recent trends in miniaturization and additional functions have meant that progress has been only in the directions of VLSIs and higher levels of integrations, making the design of microcomputers even more difficult.
Increases in wiring resistance and capacity have not only produced signal propagation delays, they also cause deformation of the rectangular waveforms of signals. There have been recent advances in lower power consumptions, particularly in portable electronic equipment, but if voltage levels become lower and the extent of deformation of the rectangular waveforms increases, it is no longer possible to ensure the functions of signals and erroneous operation can occur.
An objective of the present invention is to provide an information processing system that enables a system that can compute to any desired precision, using a simple hardware structure.
Another objective of the present invention is to provide an encryption/decryption system that makes it possible to facilitate the construction of a system that is required to operate at any desired precision (any desired number of bits), using hardware.
A further objective of the present invention is to provide an information processing system and an encryption/decryption system that make it possible to improve the effective yield when the system is configured on a single chip, and also improve the reliability of the system.
Yet another objective of the present invention is to provide an information processing system and a system LSI, together with electronic equipment using the same, in which signal propagation delays are reduced to a degree such that changes in signal waveform can be ignored, and which can be designed simply.
A still further objective of the present invention is to provide a system LSI, together with electronic equipment using the same, that make it possible to simplify the management of intellectual property rights when using the above encryption/decryption system in a simple manner, even when it incorporates functional blocks developed by other companies.
One aspect of the present invention relates to an information processing system in which computational processing is performed on input data in accordance with a processing sequence, for outputting data, the information processing system comprising:
a plurality of arithmetic units, each computing to an arithmetic precision of 2m bits (where m is, a natural number), based on the processing sequence; and
a plurality of cascade connection terminals for cascading the arithmetic units each other,
wherein, when the maximum arithmetic precision that is required during computational processing is 2n bits (where n is a natural number and is fixed), x numbers of (where x is a natural number) the arithmetic units are cascaded in a manner such that the inequality xxe2x89xa72n/2m is satisfied.
This aspect of the invention simplifies the hardware processing by distributing the computational processing among a plurality of computational processing units, making it possible to configure a system in a simple manner and increase the speed of computational processing, even when high-volume computations and large precisions are required for processing such as that for random number generation, wavelet transformation, fast Fourier transformation, and digital filters. As a result of this distributed processing, it is possible to restrain the number of gates of the arithmetic units, reducing device costs.
In this aspect of the invention, when an arithmetic precision of 2n1 bits (where n1xe2x89xa6n, and n1 is variable) is required during computational processing, x1 numbers of the arithmetic units are cascaded in a manner such that the inequality x1xe2x89xa72n1/2m (where x1 is a natural number and is variable) is satisfied. In this case, a clock generation circuit generates 2n1 numbers of reference clock pulses during computational processing. This ensures that x1 out of the x numbers of arithmetic units can be cascaded efficiently. With this configuration, the power that would be consumed by the remaining arithmetic units is saved and computational speeds are also increased. If the configuration is such that optical signals are transmitted between the plurality of arithmetic units, the computational speeds can be further increased.
Each of the plurality of arithmetic units may comprise y numbers of arithmetic modules (where y is a natural number and is fixed), each computing at an arithmetic precision of 2m/y when y numbers of the arithmetic modules are cascaded.
When an arithmetic precision of 2n1 bits (where n1xe2x89xa6n, and n1 is variable) is required during computational processing, the y numbers of arithmetic modules may be cascaded in a manner such that the inequality y1xe2x89xa72n1/2m/y (where y1 is a natural number and is variable) is satisfied.
Alternatively, computations may be executed by (x1xe2x88x921) numbers of cascaded arithmetic units at an arithmetic precision of 2n2 (where n2 less than n1) for performing computations at a 2n1-bit precision; and y1 numbers of arithmetic modules in one other arithmetic unit, which is cascaded from the (x1xe2x88x921) numbers of arithmetic units, may be cascaded in a manner such that the inequality y1xe2x89xa7(2n1xe2x88x922n2)/2m/y (where y1xe2x89xa6y, and y1 is variable) is satisfied.
If the configuration is such that optical signals are transmitted between the maximum y arithmetic modules, the computational speeds within the arithmetic units can be further increased.
This aspect of the invention could be further provided with a first storage section for storing a processing sequence. In addition, it could be further provided with computation control means for controlling the plurality of arithmetic units based on the processing sequence stored in the first storage section. In such a case, the optical signals may be transmitted between the plurality of arithmetic units and the computation control means.
This aspect of the invention could further comprise a second storage section for temporarily storing computation results of the plurality of arithmetic units, where optical signals are transmitted between the second storage section and the plurality of arithmetic units.
To give an example of the computations performed by the plurality of arithmetic units, when the input data is X and N and output data is Y, Y=X2 mod N is computed to generate a pseudo-random number.
In this case, when the yield of the plurality of arithmetic units is A and the total number of arithmetic units that are available is K, a maximum number x (where xxe2x89xa7K/A) of the arithmetic units that are operative may be cascaded.
Alternatively, when the yield of the arithmetic modules is Axe2x80x2 and the total number of arithmetic modules provided in each of the plurality of arithmetic units is L, a maximum number y (where yxe2x89xa7L/Axe2x80x2) of the arithmetic modules that are operative may be cascaded.
Another aspect of the present invention relates to an information processing system in which computational processing is performed on input data in accordance with a processing sequence, for outputting data, the information processing system comprising:
a plurality of internal arithmetic units, each computing to an arithmetic precision of 2m1 bits (where m1 is a natural number and is fixed), based on the processing sequence;
a plurality of external arithmetic units for computing to an arithmetic precision of 2m2 bits (where m2 is a natural number and is fixed); and
cascade connection terminals for cascading the plurality of internal arithmetic units and the plurality of external arithmetic units,
wherein, when the maximum arithmetic precision required during computational processing is 2n bits (where n is a natural number and is variable), z numbers of the external arithmetic units are cascaded in a manner such that the inequality zxe2x89xa7(2nxe2x88x922m1)/2m2 (where z is a natural number and is fixed) is satisfied.
This configuration makes it possible to expand the arithmetic precision in a simple hardware manner, ensuring the reliability of the system while simplifying the design of the information processing system.
An encryption/decryption system in accordance with a further aspect of the present invention comprises:
a plurality of power residue arithmetic units; and
a plurality of cascade connection terminals for cascading the plurality of power residue arithmetic units,
wherein each of the plurality of power residue arithmetic units comprises:
a multiplication unit for performing a multiplication at a multiplication precision of 2m bits (where m is a natural number and is fixed); and
a division unit for performing a division at a division precision of 22xc3x97m bits,
wherein, when the maximum arithmetic precision of a power residue computation executed by the plurality of power residue arithmetic units is 2n (where n is a natural number and is fixed), x numbers of the plurality of power residue arithmetic units are connected together for encryption and decryption, in a manner such that the following inequality is satisfied:
xxe2x89xa72n/2m (where x is a natural number and is fixed).
This configuration simplifies the processing of the hardware by distributing the computational processing required for encryption or decryption among a plurality of computational processing units, making it possible to configure a system in a simple manner and increase the speed of computational processing, even when high-volume computations and large precisions are required for the processing. As a result of this distributed processing, it is possible to restrain the number of gates of the arithmetic units, reducing device costs.
An encryption/decryption system in accordance with a still further aspect of the present invention comprises:
a plurality of internal power residue arithmetic units for performing power residue computation at a multiplication precision of 2m1 bits (where m1 is a natural number and is fixed) and a division precision of 22xc3x97m1 bits;
a plurality of external power residue arithmetic units for performing power residue computation at a multiplication precision of 2m2 bits (where m2 is a natural number and is fixed) and a division precision of 22xc3x97m2 bits; and
cascade connection terminals for cascading the pluralities of internal and external power residue arithmetic units,
wherein, when encryption and decryption is performed at a maximum bit precision of 2n (where n is a natural number and is fixed), z numbers of the external power residue arithmetic units are cascaded in a manner such that the following inequality is satisfied:
zxe2x89xa7(2nxe2x88x922m1)/2m2 (where z is a natural number and is fixed).
This configuration makes it possible to extend the arithmetic, precision for power residue computations in a simple hardware manner, making it possible to ensure sufficient reliability for the precision of the key.
In addition, since external power residue arithmetic units can be configured with a small number of gates, it is possible to simply construct an encryption/decryption system that can run on even a personal computer system.
Yet another aspect of the present invention relates to an information processing system comprising a plurality of functional units, each operating based on multi-channel electrical signals, and a bus line for transmitting signals therebetween, wherein:
each of the plurality of functional units comprises a signal output section and/or a signal input section;
the signal output section comprises electrical-optical signal conversion circuit for converting multi-channel electrical signals into multi-channel optical signals of different wavelengths, and outputting the same;
the signal input section comprises optical-electrical signal conversion circuit for converting the multi-channel optical signals of different wavelengths into the multi-channel electrical signals; and
the bus line is formed by an optical transmission medium.
In this case, signal transmission between one functional unit and another functional unit is through a bus line that is an optical transmission medium, using multi-channel optical signals having separated wavelength. For that purpose, a signal output section of each functional unit comprises electrical-optical signal conversion circuit for converting multi-channel electrical signals into multi-channel optical signals, and a signal input section of each functional unit comprises optical-electrical signal conversion circuit for converting multi-channel optical signals into multi-channel electrical signals.
Since transmission between the functional units on the single-chip are optical, signal propagation delays can be virtually ignored because signal propagation is at the speed of light. As a result, there are no design restrictions caused by such signal propagation delays, making the design of the information processing system simpler.
In this aspect of the invention, one of the plurality of functional units may be a central processing unit (CPU), and the bus line may comprise a data bus line and an address bus line. The data and address bus lines are both formed as optical transmission lines.
In this case, one optical transmission medium may be used in common for the data bus line and the address bus line. Data and addresses could be transmitted not simultaneously, but in a time division manner.
In this aspect of the invention, an optical input-output section for providing optical communications with peripheral equipment is preferably connected to the bus line. With such a configuration, an optical signal that has been converted by the electrical-optical signal conversion circuit of one of the functional units within the information processing system can be sent without any further modification to the peripheral equipment and, conversely, an optical signal from the peripheral equipment can be input without any further modification to the information processing system. This also has the advantage that no noise is superimposed on optical signals and there is no need to remove noise from optical signals.
The optical input-output section for providing optical. communications with peripheral equipment preferably enables optical communications to and from the peripheral equipment, by a chip select signal transmitted from the central processing unit through the bus line. In such a case, an optical shutter or the like, which is operated by the chip select signal, could form the optical input-output section.
A yet further aspect of this aspect of the invention relates to a system LSI configured of a first semiconductor device having a first internal bus line and a second semiconductor device having a second internal bus line, connected together by an external bus line, wherein:
the first semiconductor device comprises a first signal output section and a first signal input section, and a central processing unit (CPU) operating based on multi-channel electrical signals is formed on a first substrate, with the first internal bus line;
the second semiconductor device comprises a second signal output section and a second signal input section, and a controlled unit that is controlled by signals from the central processing unit and operates based on multi-channel electrical signals is formed on a second substrate, with the second internal bus line;
each of the first and second signal output sections comprises electrical-optical signal conversion circuit for converting multi-channel electrical signals into multi-channel optical signals having different wavelengths, and outputting the same;
each of the first and second signal input sections comprises optical-electrical signal conversion circuit for converting multi-channel optical signals having different wavelengths into multi-channel electrical signals; and
the first and second internal bus lines and the external bus line are each formed by an optical transmission medium.
In case, for example, the first semiconductor device is the above described single-chip microcomputer, this configuration makes it possible for at least one functional unit that ought to be incorporated into the microcomputer to be incorporated into a second semiconductor device instead. In this case, the functional units within the first and second semiconductor devices can transmit signals to each other by light through the first and second internal bus lines and the external bus line. Therefore, functional units that are on spatially separated substrates are connected by bus lines capable of communicating at the speed of light, so that this configuration is functionally equivalent to a microcomputer incorporating a plurality of functional units sending signals to each other by light within a single chip as described above.
Thus some of the functional units that ought to be incorporated into a single chip can be placed externally thereto, which has the advantage of making it unnecessary to increase the integration. Alternatively, if it is desired to add arithmetic functions, memory or the like to a microcomputer, it is not necessary to re-design the single-chip microcomputer as in the conventional art, so that a basic microcomputer can be attached to a semiconductor device via an external bus line that is an optical transmission medium. This has the advantage of further increasing the universality of the microcomputer.
In particular, application of the present invention makes it possible to freely modify the capacity of cache memory.
More preferably, the configuration is such that an internal clock on an internal bus line can be supplied to the external bus line. This makes it possible for an internal clock to act as a reference clock for all of the functional units, so that data can be processed in synchronized mode.
Incorporating the above described information processing system or system LSI of the present invention is incorporated into electronic equipment makes it possible to support modifications of the functions of the electronic equipment.
A final aspect of in accordance with this aspect of the invention relates to a system LSI incorporating a plurality of functional blocks developed by different manufacturers, wherein:
at least one of the plurality of functional blocks comprises a four-arithmetical-operations function area; and
the four-arithmetical-operations function area executes computations for decryption when a predetermined decryption key has been input thereto, and a four-arithmetical-operations function other than the decryption is enabled after the decryption is established.
Assume that this system LSI comprises a functional block that was developed by Company A, by way of example. A decryption key (private key) in accordance with the RSA method is disclosed by license to the end user who is using the functional block developed by Company A within this system LSI. Among the users of this system LSI, only end users who possess the decryption key can use this functional block. To use the functional block developed by Company A in this configuration, it is necessary to acquire the decryption key from Company A by license, simplifying the management of intellectual property rights.
The four-arithmetical-operations function area could also comprise x numbers of arithmetic units, each having an arithmetic precision of 2m bits (where m is a natural number and is fixed), that are cascaded for computations. A portion of the plurality of arithmetic units could comprise a plurality of power residue arithmetic units that are cascaded.